Purists will argue that the real millennium, and the real 21st century, won't start until January 2001. Regardless of when the new century actually starts, we're heading into a challenging new world for chip design tools and methodologies.

The big story for EDA in the 1990's was the move from gate-level to RTL design. By simple extrapolation, we can predict that the big story for the next decade will be the move to electronic system-level design, or what Dataquest's Gary Smith calls "ESL" (see Smith's article, "The Dream-Communications/Core-Based Design," on page 20) in this issue. That will be true to a great extent, but the actual picture isn't so simple. We must add an additional question-system-level design of what?

For the last 20 years, even though a handful of tools have addressed full-custom chips and we've seen increased tool support for complex programmable-logic devices (CPLDs), the ASIC design methodology has driven the EDA industry. Over time, a very clear, well-understood tool chain has emerged. We do behavioral modeling, write RTL code, and run simulation or formal verification. We synthesize to gates, do placement and routing, run verification, and hand it off to the fab.

Over the next decade, the traditional ASIC approach will be just one of several ways to get products to market. A radically different approach may be found with programmable, platform-based system-on-a-chip (SOC) devices. These application-specific devices will include a pre-selected processor, RTOS, bus structure, and some peripheral blocks. Differentiation will be through embedded software and programmable or reconfigurable hardware. The latter may come in the form of embedded FPGA logic, or something more exotic; the key point is that such devices may not require any custom silicon design.

Programmable SOCs will never give you the fastest possible performance or smallest die size. But they will let you get architectural variants out the door very quickly, which may be a much more important concern. Moreover, dynamically reconfigurable architectures can potentially provide much more flexibility than any ASIC.

The tool chain for programmable SOCs will be very different. Consider Nimble Compiler, the subject of an advanced research project headed by Synopsys.

This ANSI C compiler extracts computationally intensive loops and loads them into a reconfigurable datapath. The rest of the code is compiled into an embedded processor. There's no synthesis, no RTL verification, no place and route. There's no real notion of "hardware" or "software." It is, in fact, pure ESL design.

At the other extreme, some people will care about squeezing the last nanosecond out of a piece of silicon. And here, you may see a shift towards what looks like more of a full-custom approach. At the very least, RTL design and layout will be so coupled as to be almost one process. And rather than use an ASIC vendor's cell library, many designers will generate and characterize their own, using automated tools. Don't forget, we'll need a lot of analog and mixed-signal design as well, and that doesn't lend itself to an RTL ASIC approach.

FPGAs will be large and fast enough to replace ASICs in some applications. FPGA designers will move up to an RTL ASIC-like design flow, if they haven't already. But with multi-million gate FPGAs on the near horizon, they won't stop there. They, too, will move up to ESL design, and find themselves in a world where the separation between "hardware" and "software" gets very blurry.

So there you have it. ASICs aren't going away completely, but the time-worn RTL ASIC design flow is diverging in several different directions. Some of today's ASIC designers will move up to ESL tools. Others will move down to custom silicon implementation.

Some might migrate into the embedded software world, or into the ambiguous world of not-quite-hardware, not-quite-software programmable or reconfigurable SOC design.

And if you think this is interesting, wait another decade or so, when we may be building computers out of DNA molecules or optical switches or nanotechnology.